The TeraDIMM can be configured in one of two ways. What Diablo has done is build a specialized translation ASIC (codenamed Rush) and implemented it on-board a standard DIMM. ThatвЂ™s the reference design - the company has partnered with SMART Storage Systems to bring actual product to market. TeraDIMM TechnologyДiablo calls its own particular implementation of this technology TeraDIMM. The companyвЂ™s Memory Channel Storage connects huge (200-400GB) pools of storage directly off the memory bus with ultra-low latency and better performance characteristics.

Diablo has something rather interesting here. NAND isnвЂ™t designed to be read or written in the same fashion, and it takes far longer to perform a read/write cycle to flash than it does to DRAM.ДЄfter talking to the company, I think my skepticism was misplaced. DRAM and NAND flash are designed for entirely different purposes, starting with the fact that DRAM is volatile, while NAND flash isnвЂ™t. ThatвЂ™s why I was initially skeptical when Diablo Technologies claimed to have found a way to drop NAND flash into the main memory bus of a system. The problem is that even pulling data from е…ѓ has a noticeable impact on a chipвЂ™s performance - going to main memory takes hundreds of cycles, while accessing primary storage takes tens of thousands. If a chip canвЂ™t find data in cache, it has to go out to main memory and from there to storage. Thus, a typical CPU has a small, low-latency L1 cache, a larger, slower L2, and so on. Larger, slower memory pools are far cheaper, but canвЂ™t be searched as quickly and take time to access. The problem, in a nutshell, is that fast, low-latency memory is extremely expensive and canвЂ™t hold much information. One of the most fundamental problems in computing is the relationship between a CPU and its memory hierarchy.

Diablo 2 rush channel